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High-Speed Digital Applications

Breaking the High-Speed Barrier

High-speed digital interfaces for the computer, consumer and communications markets have moved forward dramatically. These rapid improvements in speed and performance have created significant test challenges, requiring major changes in test methodologies and in many cases true cross-domain test approaches.

• Ethernet is approaching 10Gbps on its way to 40Gbps and 100Gbps. Peripheral Component Interface (PCI express) is moving from 2.5Gbps to 5Gbps with a short-term roadmap of 8Gbps and 10Gbps.
• Serial Advanced Technology Attachment (SATA) is moving from 1.5Gbps to 3Gbps with a roadmap to 6Gbps. Other network interfaces such as XAUI are already at 10Gbps and moving to 12.5Gbps, with 25Gbps on the horizon.
• HDMI multimedia interface is moving from its current multi-channel 1.65Gbps to 3.3Gbps. And USB3 is headed towards 4.9 Gigabit/second speeds.
• Memory interfaces are also increasing; Double Data Rate (DDR) architectures are currently running at 800Mbps and quickly moving to 1.6Gbps and 2.4Gbps and then on to 3.2Gbps, 6.4Gbps and further out 8Gbps and 16Gbps

Contactor Value

Any contactor solution must provide the necessary electrical performance required to sustain the value economics in a production environment. Value in this case is improving test throughput and cost efficiency for high performance lead-free devices, which are dependent on three major factors, test cell availability, test throughput and first pass yield quality.

Johnstech International builds products that provide superior electrical characteristics and production level mechanical performance in a lead-free environment. The result is a high performance, high reliable and low cost-of-test solution that provides a high level of customer value for high-speed digital interface semiconductor applications.

What Makes High-Speed Digital a Challenge?

To guarantee measurement quality of a Device Under Test’s (DUT) transmit and receive signals, the interface and test instrumentation should have a bandwidth equivalent to the third harmonic of the highest frequency of interest, and in some instances the fifth harmonic.

For a 10Gbps digital signal the highest code frequency is a mark space clock type pattern, which at 10Gbps represents a 5GHz cycle/period; however, a digital signal is comprised of many frequency components (Figure 1), where the true level of speed is governed by the edge rise and fall time equivalent frequency. Therefore, the maximum bandwidth required is determined by these rise and fall times and not the base period frequency.

At 10Gbps the rise and fall times can be as low as 20ps. A bandwidth calculation from rise time is exemplified using the calculation of rise time of a step response for simple systems. To convert this rise and fall time into its -3dB equivalent bandwidth use the well known formula BW= 0.34/rise time.

At 20ps this would indicate a fundamental -3dB frequency of 17.5GHz and a third harmonic bandwidth of 52.5GHz; not the 15GHz associated with a 5GHz sine wave, or the 5GHz pulse period. For differential signals a bandwidth equal to 1.8 times the rise time frequency is in most cases acceptable.

In this case a differential signal bandwidth of less than the 31.5GHz will tend to filter and roll off the device’s signal edges. This would result in a reduced rate of change of the rising and falling edge slope; a condition that converts more of the devices random noise into jitter at the transition points, and effectively closes down the signal eyes waveform tolerance (Figures 2 & 3). As a result, good devices could potentially fail, reducing yield, revenue and profit.