How to Improve OEE with Contactor Maintenance and Set-Up Checks
by Eugene Batilo, Sales Engineer
Understanding Specs to Better Simulate Solder-to-Board Performance
Presented at the BiTS Workshop, March 2012
by: Jeff Sherry, PE, MSEE, Senior RF Engineer
Configurable Kelvin Technology for Test Optimization
by Jeff Sherry, PE, MSEE
CCC: What is it and Why is it Important to Your Test Times and Yields?
by Harlan L. Faller, PE, MSEE and Jeff Sherry, PE, MSEE
Monte Carlo Simulation and Design of Experiments for Improved Pin-Pad Alignment
Presented at the BiTS Workshop, March 2011
by: John DeBauche, Engineer Manager
Can Your Socket Handle the Heat?
Published in Chip Scale Review, March 2011
by: Jeff Sherry, PE, MSEE, Senior RF Engineer
Thermal Modeling and Analysis of Device-Contactor-Load Board System
by Harlan Faller, PE, Advanced Senior Technologist
Choosing Pulse Parameters for High Current Testing
by Harlan L. Faller, PE, Lead
Designing the Optimal Board for IC Testing
Published in EE-Evaluation Engineering, September 2010
By Jeff Sherry, PE, MSEE, Senior RF Engineer
Pulsed Current-Carrying Capacity of Small Metallic Conductors as applied to Device Test
Presented at the BiTS Workshop, March 2009
Attendee Choice Award Winner
Cost of Test is not the only Factor to Consider in Production Test
Published in Chip Scale Review, November 2008
Socket Performance Over Time & Insertion Count with Pb-Free Applications
Presented at the BiTS Workshop, March 2006
Award Winning Paper: Best Data Presented
Resolving test challenges for emerging wireless designs
Understanding How Pb-Free Platings Affect Production-Test Cost, Throughput and Yield
Challenges of Contacting Lead-Free Devices
RF Wireless and High Speed Digital Test Issues and Your Contactor Supplier
Orchestrating Four ATE Suppliers To Reduce Test Cost For A High-Volume RF-IC
Optimizing the Whole Test System to Achieve Optimal Yields and Lowest Test Costs *
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